The invention relates to a current divider for dividing a first signal current into a second and a third signal current, which current divider comprises a first terminal for the passage of the first signal current, a second terminal for the passage of the second signal current and for receiving a first potential, a third terminal for the passage of the third signal current and for receiving a second potential, at least a first element coupled between the first terminal and the second terminal, and at least a second element coupled between the first terminal and the third terminal.
The invention also relates to an integrated circuit comprising a plurality of current dividers.
In the present document a signal current is to be understood to mean a current resulting from an input current applied to a current divider, the first and the second element carrying, besides the respective signal currents, a bias current determined by the first and the second potential.
Such a current divider is suitable for general use in integrated circuits, which integrated circuits can be constructed, for example, as a volume control or as a digital-to-analog converter.
Such a current divider in which the first and the second element are realised by means of a first and a second resistor respectively is generally known. In the current divider implemented by means of the first and the second resistor an input current applied to the first terminal and corresponding to the first signal current is divided in accordance with a ratio dictated by a resistance value represented by the first and the second resistor.
A disadvantage of the current divider realised by means of the first and the second resistor is that the resistors occupy a comparatively large semiconductor area in an integrated circuit and the resistance values, which are influenced by parasitic effects, give rise to a usually non-linear and comparatively inaccurate current division. The relevant parasitic effects occur particularly when a transistor switch for switching the respective signal currents is coupled in series with both the first and the second resistor, which switch exhibits a conductance which varies depending upon the respective signal current.